Semiconductor fabrication faces shrinking device dimensions and increasing process complexity. Devices of today are smaller and require more fabrication processes than devices of even a few years ago. Additionally, the shrinking dimensions require ever tighter tolerances for performance of the process employed in semiconductor fabrication.
Semiconductor manufacturers generally recoup their manufacturing costs by selling their fabricated semiconductor devices. However, some semiconductor devices fail to meet operational requirements and are, therefore, unable to be sold. As a result, the manufacture does not recoup the manufacturing costs for the failed devices.
A critical statistic in semiconductor fabrication is yield, which is a percentage of devices fabricated that meet operational requirements. A goal of device fabrication process is to reach 100 percent yield, although this goal is not generally obtained. However, the closer to this goal and the higher the yield, the greater the profitability for the manufacturer.
Semiconductor fabrication processes and the devices themselves are very sensitive to out of tolerance process conditions, mishandling, movement, temperature, humidity, and the like. As a result, defects in structures and layers present in semiconductor devices can occur.
An important step in the manufacture of integrated circuits is the formation of metal conductors, which provide electrical connections to devices formed therein. Conductors in integrated circuits are typically formed of copper metallization, in order to take advantage of the lower resistance of copper (though aluminum is also used in certain cases). The minimum line width is sought to be minimized, since it is often a factor upon which the overall integrated circuit chip area depends. In order to minimize the chip area required for realization of complex integrated circuits such as digital signal processors (DSPs) or microprocessors, multiple metallization levels are common in the art, despite the complex manufacturing processing required for their fabrication.
Voiding in metal conductors is an important defect that can occur in the fabrication of thin, closely-spaced, metal conductors, particularly in multiple layers. Voids may be caused in the deposition of the metal film, as a result of metal etch, or by unintended corrosion during processing. Voids can also be caused by migration of atoms during thermal processing under stress fields that develop over the metal line, or due to electrical currents; voids in metal conductors can also be present because of the inability of large grains to fill gaps, particularly in small geometries and over topography. Because of the yield loss due to defective metal lines, and also considering later-life reliability hazards resulting from the void, the prevention and/or mitigation of voids in metal conductors is important in modern integrated circuit manufacturing.
In previous years with larger devices, metal voids could be readily detected by optical inspection (automated or otherwise) of the integrated circuits during or after their manufacture. Additionally, the reduction in metal conductors to the sub-micron range has not only reduced the optical visibility of the conductors, but also reduced the minimum size of a killing void further below the visibility of optical microscopy. In addition, the presence of voids within the body of a conductor line generally cannot be detected by visual or scanning electron microscopy (SEM) techniques that are currently in use. Particularly in damascene copper structures, voids are sometimes buried, and are thus optically invisible, regardless of the conductor dimensions. The implementation of multiple metal levels has also limited optical inspection, because the ‘noise’ introduced by the grains in the underlying metal level reduces the efficacy of automated inspection of the top-most metal at any particular point in the fabrication sequence.
As a result, at least some conventional void detection relies upon destructive techniques. Typically, sample wafers from the manufacturing line are cross-sectioned, and the cross-sections are examined by SEM for a measure of the metal film quality. The destructive nature of this inspection reduces the number of samples that may be inspected by SEM. Furthermore, the nature of SEM precludes the viewing of more than a small number of locations of the wafer within each sample. The preparation of the cross-sectional samples for SEM analysis is also time-consuming, and thus costly. As such, routine SEM inspection is not a very effective, feasible measure of the metallization film quality.
Some other techniques are currently being developed for measuring the quality of metallization films. Magnetic force microscopy measures variations in magnetic flux caused by voids in the metallization; of course, this measurement not only requires current to be conducted through the conductor during measurement, but also highly precise magnetic field detection elements. Surface acoustic wave (SAW) microscopy has also been proposed, in which variations in reflection of acoustic waves due to voids may be measured, but resolution considerations tend to limit the applicability of SAW microscopy to small geometries. Additionally, some of the proposed methods utilizing SAW microscopy essentially rely upon ‘golden’ structures that are void-free but otherwise identical to the conductor structure being inspected, which is an onerous stipulation.